Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
About the role
The Principal Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role combines hands-on silicon bring-up and debug with technical leadership of validation activities, including test planning, methodology, and coordination across design, DFT, firmware, and product/test engineering. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Typically 5+ years of industry experience in silicon or system validation, including hands-on lab work
- Strong expertise in at least two of the following: CXL (2.0/3.x), PCIe (Gen4/Gen5/Gen6), DDR (DDR4/DDR5), HBM (HBM2/2E/3), high-speed SerDes
- Proven experience leading bring-up and validation of complex ASIC/SoC products from first silicon through production
- Deep hands-on experience with lab equipment (oscilloscopes, protocol analyzers, logic analyzers, BERTs, power supplies, etc.) and high-speed measurement techniques
- Strong scripting and lab automation skills (e.g., Python, TCL, shell, MATLAB) for test control and data analysis
- Demonstrated ability to drive cross-functional debug and closure, with clear communication of complex technical issues
More about this role
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
The Principal Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role combines hands-on silicon bring-up and debug with technical leadership of validation activities, including test planning, methodology, and coordination across design, DFT, firmware, and product/test engineering.
- Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces, covering functionality, performance, power, margining, and interoperability.
- Lead silicon bring-up and lab...
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