We make the best chips physically possible for the large model needs of frontier labs.
About the role
Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, and fullchip design Own entire subsystems or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off-ready design Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- At least 5 years of silicon design experience
- Tape-out experience — you have taped out chips, demonstrating end-to-end ownership of a design through multiple generations
- Ability and willingness to ramp on Bluespec — a functionally-rooted HDL used for our designs. Prior Bluespec, or familiarity with functional-programming paradigms (e.g. Haskell), is a plus
- Production-proven experience with silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related functionalities
- Experience with SystemVerilog, Python, C/C++, and similar scripting and programming languages for chip design and related flows
- Experience testing your designs and working closely with verification teams toward performance and coverage closure goals
More about this role
MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.
The compute subsystem implements all of the core numerics and the associated control and data paths required to realize meaningful hardware acceleration of our target ML workloads. In this role you own the micro-architecture and RTL for blocks within it, end to end.
Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, and fullchip design
Own entire subsystems or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off-ready design
Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, and area and timing closure toward various silicon milestones including design freeze and tapeout
Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results
At least 5 years of silicon design experience
Tape-out experience — you have taped out chips, demonstrating end-to-end ownership of...
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