Micron is a global leader in memory and storage, powering AI and compute-intensive applications from cloud to edge with innovative semiconductor solutions.
About the role
As a Principal Design Engineer on the NAND datapath team, you will lead architecture and design of the internal datapath between the page buffer and IO: wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair and clocking. You will use AI daily to accelerate design, timing closure and verification, help bring STA-based semi-custom methodology into a simulation-only flow, and set technical direction as a recognized leader! Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- 8+ years in memory datapath, SRAM or high-speed custom design
- BS/MS in EE or related field
- Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin)
- Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification
- Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation
- Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes
More about this role
Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Micron’s Non-Volatile Engineering Group (NVEG) develops best-in-class NAND memory products in die size, performance, reliability and power! NVEG is embedding AI across the entire design flow, and we are looking for engineers who use AI daily and actively reshape engineering workflows around it.
As a Principal Design Engineer on the NAND datapath team, you will lead architecture and design of the internal datapath between the page buffer and IO: wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair and clocking. You will use AI daily to accelerate design, timing closure and verification, help bring STA-based semi-custom methodology into a simulation-only flow, and set technical direction as a recognized leader!
- Datapath architecture: Define, design and verify internal datapath blocks (page buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES front ends...
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