Micron is a global leader in memory and storage, powering AI and compute-intensive applications from cloud to edge with innovative semiconductor solutions.
About the role
We are seeking a Principal IO/Clocking Design Engineer to be a part of our design team working on critical high-speed circuits common to all DRAM related memory products! In this position, you will be responsible for the development, design, optimization, verification, and fan out of these high-speed circuits to all DRAM related projects at Micron. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Minimum MSEE + 10 years or BSEE + 12 years of industry experience in analog and mixed-signal circuit design
- Proficiency with UNIX and CADENCE design environment (simulation, schematic entry, SPF extraction)
- Understanding of device physics and basic CMOS processing techniques
- Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts
- Strong communication skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written
- Mental agility is a must for this position as we work with all product types (commodity, mobile, graphics) and product teams in parallel with silicon validation efforts
More about this role
Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
We are seeking a Principal IO/Clocking Design Engineer to be a part of our design team working on critical high-speed circuits common to all DRAM related memory products! In this position, you will be responsible for the development, design, optimization, verification, and fan out of these high-speed circuits to all DRAM related projects at Micron. You will work on equalization and bandwidth extension to push the speed limits of the circuit and process technology, analyze resulting IO impairments, clock jitter and duty error impact to DRAM system and timing budget, and develop effective engineering solutions.
- Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
- Apply proven high-speed circuit design techniques and enhance critical performance evaluation of the IO data path and clocking path at circuit level.
- Develop accurate...
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