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Senior CAD Engineer – Physical Verification

Micron Technology · 2 Locations · On-site

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About Micron Technology

Micron is a global leader in memory and storage, powering AI and compute-intensive applications from cloud to edge with innovative semiconductor solutions.

About the role

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent
  • 5+ years of industry experience in CAD, EDA, or semiconductor design
  • Experience with DRC and LVS physical verification , IC layout, and process design rules
  • Ability to interpret design-rule requirements and resolve complex verification issues in production flows
  • Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting
  • Solid CMOS and VLSI fundamentals , with clear communication and practical debugging skills across global teams
More about this role

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

  • Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
  • Develop, debug, qualify, and release Siemens Calibre design rule checking (DRC) and layout versus schematic (LVS) rule decks using Standard Verification Rule Format (SVRF).
  • Translate process design rules into verification checks, and define the test cases, coverage criteria, and regression methods that qualify them.
  • Partner with process, design, layout, modeling, and verification teams to define signoff strategies and resolve verification issues.
  • Guide design teams on verification methodologies, waivers, and debugging, and provide training, documentation, and production support.
  • Evaluate EDA technologies that improve verification quality, performance, and capacity.
  • Automate verification setup, execution, and reporting, including AI-assisted...

Read the full posting on Micron Technology's site ↗

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