Micron is a global leader in memory and storage, powering AI and compute-intensive applications from cloud to edge with innovative semiconductor solutions.
About the role
Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership. Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization.
What they're looking for
- 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes
- Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands‑on ownership of verification closure
- Proven experience in layout of critical analog blocks, including but not limited to Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps, etc
- Hands‑on experience with memory layouts, including DRAM, SRAM, CAM, OTP and understanding of array‑to‑periphery integration
- Deep understanding of analog layout fundamentals, including Matching and symmetry, EM, latch‑up, coupling, crosstalk, IR‑drop, shielding, guard‑ring strategies, parasitic effects
- Strong ability to interpret design intent and constraints and translate them into high‑quality, manufacturable layouts
More about this role
Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Job Description
Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership.
Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization.
Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.
Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans.
Develop and deploy AI‑enabled methodologies for Semi-automated floorplanning, parasitic estimation, layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows.
Demonstrate technical...
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