Micron is a global leader in memory and storage, powering AI and compute-intensive applications from cloud to edge with innovative semiconductor solutions.
About the role
Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Strong hands‑on experience with SoC develop for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG
- Experience working across full RTL‑to‑GDS SoC flows and collaborating with synthesis, static timing analysis (STA), and physical design teams
- Proficiency using industry‑standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience
- Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital application‑specific integrated circuits (ASICs) or SoCs
- Experience with large, complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems
More about this role
Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry.
You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up...
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