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Senior Silicon Design Verification Engineer

Microsoft · Mountain View, CA, US · On-site

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About the role

The candidate for this position will be expected and able to complete the following responsibilities: Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors. Extend the compile and build flow to support custom firmware-style tests. Serve as a technical owner for the team's FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files.

More about this role

The candidate for this position will be expected and able to complete the following responsibilities: Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors. Extend the compile and build flow to support custom firmware-style tests. Serve as a technical owner for the team's FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files. Design additional custom FPGA RTL for protocol interfaces and feature enablement. Release stable platforms to the firmware team and keep them working as the design evolves. Develop and extend custom python tooling to interface with the FPGA platform. Debug FPGA and post-silicon issues using tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters Drive post-silicon bring-up and validation in the lab: run the validation suites on first silicon, meet bring-up exit criteria on schedule, and debug platform issues such as JTAG failures, UART connectivity, and boot failures alongside the design, firmware, hardware, and security teams. Root-cause failing post-silicon tests to closure, collecting...

Read the full posting on Microsoft's site ↗

Silicon Engineering

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