Creating a generalized brain interface to restore autonomy to those with unmet medical needs today and unlock human potential tomorrow. Backed by Lightspeed, Sequoia and Founders Fund.
About the role
We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- BS/MS in Electrical/Computer Engineering (or equivalent) with 5+ years of physical design experience, MS preferred
- Proven full-cycle RTL-to-GDSII experience on advanced nodes (7nm/5nm/4nm/3nm or comparable)
- Hands-on hierarchical/top-level implementation on large (multi-million instance) designs
- Strong command of STA concepts (setup/hold, OCV/AOCV/POCV, MMMC) and physical verification signoff
- Proficiency with industry PnR and signoff tools (e.g., Cadence Innovus/Genus/Tempus/Voltus, Synopsys ICC2/Fusion Compiler/PrimeTime/StarRC, Siemens Calibre) and TCL scripting
More about this role
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure.
- Define and execute the hierarchical partitioning strategy: block boundaries, feedthroughs, pin placement, and budgeting across levels of hierarchy.
- Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs.
- Own the interface between block owners and top-level integration, including abstract (ILM/ETM) generation, boundary timing, and hierarchical ECO propagation.
- Manage die-to-die partitioning for 3D stacks – assign logic to...
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