NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
Depending on your interests and team placement, you'll contribute to one or both of the following: Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- BS or MS in Electrical/Computer Engineering, Computer Science, or equivalent practical experience (recent or upcoming graduate)
- Coursework or project experience in digital logic and computer architecture — pipelines, out-of-order execution, branch prediction, or similar topics
- Proficiency in C/C++, SystemVerilog, and/or Verilog, plus familiarity with a scripting language (Python preferred, Perl a plus)
- Exposure to functional verification concepts (testbenches, checkers, coverage) or RTL design/coding, through coursework, internships, or personal projects
- Strong fundamentals in CPU micro-architecture concepts
More about this role
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. We are seeking new college graduates to join our CPU team, contributing to either Design Verification (DV) or RTL/micro-architecture design. You'll work shoulder-to-shoulder with architects, RTL designers, and verification engineers across units including fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and the multi-level cache subsystem — helping build and prove out a CPU that targets industry-leading power, performance, and area.
Depending on your interests and team placement, you'll contribute to one or both of the following:
Design Verification
- Help build test plans, environments, stimulus generators, checkers, transactors, and coverage that exercise the CPU pipeline end to end.
- Write and debug directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
- Partner with architects to correlate RTL against performance...
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