About the role
AI and Chip Engineering SoC Implementation team is seeking a passionate technologist who thrives in solving complex problems for the role of Static Timing Design Manager. As STA Manager, you will be managing a team of motivated engineers working on the AI, Edge and Automotive Processors in NXP. You will be working on fast paced, and leading-edge advanced node technologies building exciting and complex SoCs.
What they're looking for
- BS or MS in Electrical or Computer Engineering
- 15+ years of experience in Physical Design for complex SoCs
- Experience with at least 3 years of STA Lead roles
- Excellent communication skills, both oral and written
- Innovate and adapt to the rapid use of AI and agents in STA & PD domains
More about this role
AI and Chip Engineering SoC Implementation team is seeking a passionate technologist who thrives in solving complex problems for the role of Static Timing Design Manager. As STA Manager, you will be managing a team of motivated engineers working on the AI, Edge and Automotive Processors in NXP. You will be working on fast paced, and leading-edge advanced node technologies building exciting and complex SoCs. You will be a major influence in the development, and support of the SoC implementation organization’s charter to build world-class MPUs.
- Expertise in developing, implementing and verifying STA constraints
- Expertise in efficient closure of Subsystem as well as SoC-level timing
- In-depth knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
- Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
- Contribute to timing flow and methodology improvements
- Collaborate with members of a global design team to complete large SoC (system-on-chip) projects.
- Partner with Architecture and RTL teams to influence early design decisions
- Ability to coordinate with all...
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