About the role
We are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor products. This role will own end-to-end Timing Constraints and Static Timing Analysis across complex designs, driving initial constraints development and timing correlation in early stages to final Timing Signoff for cutting-edge technology nodes. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor’s or Master’s in Electrical / Electronics Engineering or related field
- 3-6 years of experience in ASIC / SoC Timing Analysis
- Strong knowledge of industry STA tools (Synopsys flows)
- Strong communication skills
More about this role
We are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor products. This role will own end-to-end Timing Constraints and Static Timing Analysis across complex designs, driving initial constraints development and timing correlation in early stages to final Timing Signoff for cutting-edge technology nodes. This role would work with implementation engineers from synthesis through final timing closure to close timing, including timing correlation, debugging failing timing paths, providing timing ECOs (automated and manual).
The ideal candidate demonstrates technical timing and constraints expertise to close timing on a given design on silicon along with capability of using timing analysis tools to correlate timing and generate automate as well as manual timing fixes.
- Drive Timing Constraints Creation and Validation
- Work with Frontend, IP and DFT teams to Validate Constraints, Resolve timing issues
- Work hand-in-hand with Implementation owner(s) and Full Chip STA team to close Timing
- Timing Correlation and Timing Path Debug from synthesis through timing signoff
- Provide timing feedback during all design stages
- Create Automated and Manual...
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