About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Backed by NEA.
About the role
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Define and document microarchitecture for complex IP blocks/subsystems
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up, collaborate with PD on floorplan and timing closure
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR)
- Engage with IP vendors and internal stakeholders to ensure seamless integration
More about this role
Role Overview
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.
Key Responsibilities
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Engage with IP vendors and...
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