About Positron AI Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Backed by NEA.
About the role
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- A BS, MS, or PhD in Electrical Engineering or Computer Engineering
- 8+ years of ASIC development experience
- Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts
- Deep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis
- Hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required
- Strong RTL design skills using Verilog/SystemVerilog
More about this role
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role.
Hands-on DFT Implementation
- Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
- Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
- Work directly in RTL, synthesis, and DFT tool flows.
Drive Pre-Silicon DFT Verification
- Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
- Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
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