Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial,...
About the role
Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power-control architectures pre-silicon — proving out control loops, catching RTL issues early, and de-risking tape-out.
What they're looking for
- Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs
- Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL
- Hands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling
- Strong command of the full FPGA implementation flow — synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) — on large Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus
- Hardware bring-up and debug experience: in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug
- Proficiency scripting for automation (TCL, Python)
More about this role
Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power-control architectures pre-silicon — proving out control loops, catching RTL issues early, and de-risking tape-out.
These FPGA platforms are emulation vehicles, not production hardware. Success is measured by how faithfully and how fast they reproduce the target silicon: functional equivalence to the golden ASIC RTL, real-time (or near-real-time) performance for closed-loop power and DSP validation, and deep visibility for pre-silicon debug.
- Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA — advising on FPGA-ability and turning architectural intent into a working, real-time emulation platform.
- Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design — handling clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state/bus conversion, and...
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