Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial,...
About the role
Are you ready to join our team and shape the future with us? Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- BSc/MSc in Electrical Engineering/Computer Engineering (EE/ECE) and 10+ years of relevant industry experience
- Prior design project work experience showing collaborative and innovative thinking
- Proficient in developing CDC / RDC / LINT clean designs in Verilog
- Comfortable with debugging mixed-signal designs in System Verilog based test benches
- Exposed to gate level simulation debug
- Experience in designing industry standard serial interfaces (I2C, I3C, SPI, I2S etc)
More about this role
Our team works on the most advanced digital power management ICs in the industry. This is an excellent full-time/permanent role giving the opportunity to work with an expert team pushing the envelope of digital design, verification, debug, simulation, and automation script development and thus contributing to industry leading chips.
Job Duties
Develop, debug, and verify digital designs in pre and post silicon environment
Write tests to verify bulk design intent as per specification.
Learn, develop and improve scripts to facilitate design automation flows.
Manage assigned design blocks in design requirements, architecture, and implementation
Research and present new tools in aid of design development process
Act as technical mentor for junior engineers.
Represent digital design as functional digital design lead in design projects.
BSc/MSc in Electrical Engineering/Computer Engineering (EE/ECE) and 10+ years of relevant industry experience
Prior design project work experience showing collaborative and innovative thinking
Proficient in developing CDC / RDC / LINT clean designs in Verilog
Comfortable with debugging mixed-signal designs in System Verilog based test benches
Exposed to...
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