About Renesas Electronics
We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs.
About the role
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What they're looking for
- Bachelor’s or Master’s degree in Electrical Engineering (PhD preferred)
- 12+ years of experience in analog/mixed-signal IC design with deep focus on high-speed memory interfaces
- 5+ years of people-management and technical leadership experience
- Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5
- Strong expertise in: High-speed IO design and signal integrity, PLL/DLL and low-jitter clocking architectures,Mixed-signal verification and silicon validation, Advanced CMOS process considerations for IOs
- Direct involvement in DDR6 architectural studies or early-stage development
More about this role
Technical Leadership (DDR5 / DDR6)
- Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
- Provide technical oversight for critical analog and mixed-signal blocks, including:
- High-speed TX/RX datapaths
- Advanced equalization, termination, and training circuits
- DLL/PLL-based clocking solutions for multi-GHz operation
- Voltage, reference generation, and power-aware IO design
- Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates.
- Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction.
- Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.
People & Organization Leadership
- Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces.
- Set technical direction, performance expectations, and development plans for senior and principal engineers.
- Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs.
- Foster a culture of technical rigor,...
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