Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial,...
About the role
Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure. Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 4 or more years of relevant digital design verification experience, or equivalent directly applicable experience
- Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure
- Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions
- Experience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria
- Hands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures
More about this role
Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications.
You will independently own verification of significant blocks and features from planning through closure. The role combines hands-on UVM development, coverage-driven verification, complex debug, and close collaboration with architecture, RTL design, firmware, analog, validation, and systems teams.
Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
Develop constrained random and targeted tests for normal operation, error handling,...
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