Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial,...
About the role
Renesas is looking for an experienced Staff Design Verification Engineer to join our team developing leading-edge memory interface products for data center, AI, and cloud computing applications. These products enable high-bandwidth, power-efficient memory solutions for intensive computing environments. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field , or equivalent experience
- 8+ years of related experience in semiconductor design verification
- Strong experience in semiconductor design verification
- Strong proficiency with SystemVerilog and hands-on experience using UVM (Universal Verification Methodology)
- Experience developing and debugging UVM-based verification environments and testbenches
- Experience with verification planning, functional verification, coverage, checkers, test development, and debugging
More about this role
Renesas is looking for an experienced Staff Design Verification Engineer to join our team developing leading-edge memory interface products for data center, AI, and cloud computing applications. These products enable high-bandwidth, power-efficient memory solutions for intensive computing environments.
This role will contribute to the verification of advanced memory data buffer products, including DDR6 and future generations . The ideal candidate brings strong semiconductor design verification experience with SystemVerilog and UVM . Previous DDR or memory experience is an advantage, but is not required.
Key Responsibilities
- Drive verification activities for complex digital designs at the block and system level .
- Develop and execute verification plans based on functional and performance specifications.
- Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches .
- Develop verification tests, functional coverage, checkers, and other verification components.
- Take ownership of verification environments and verification execution for assigned blocks and features.
- Drive and monitor coverage to ensure verification goals are achieved.
- Work...
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