We develop frontier AI methods to reinvent chip development, collapsing traditional design timelines, closing the loop between AI and the hardware that fuels it, and enabling a Cambrian explosion of custom silicon. Backed by Lightspeed, Sequoia and Felicis.
About the role
A self-improving chip design system is only as good as the silicon it produces, and silicon only counts once it has been tested, screened, and shipped. We are hiring a DFT engineer who treats testability as a first-class design discipline: someone who has architected the scan, MBIST, and boundary-scan infrastructure for complex chips at advanced nodes, generated and signed off the patterns that qualified them, and then stood at the tester when first silicon came back. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field
- Day-one fluency in at least one production DFT stack and gate-level simulation, with strong Tcl and Python scripting and enough Verilog/SystemVerilog to write and debug test logic and testbenches yourself
- Post-silicon experience on silicon that taped out and shipped to production: converted and brought up ATPG and MBIST patterns on ATE, debugged CP, FT, and SLT failures, and worked directly with foundry and OSAT partners
- Practical, demonstrated use of AI coding and agentic tools in your own engineering work, with clear ideas about where they help in a DFT flow and where they do not
- Masters or PhD in EE, CE, CS, or a related field, with a focus on VLSI test, fault tolerance and reliability, or EDA/CAD algorithms
- Deep expertise in high-performance compute silicon (e.g., ML accelerators, CPUs, GPUs, or large SoCs), including DFT for advanced packaging
More about this role
Ricursive Intelligence is a frontier AI lab building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. Backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures, we are a growing, fast-paced team where every hire shapes the work.
The company has unmatched talent density, including IMO, IPhO, and IOAA gold medalists, pioneers who made prior breakthroughs in chip design: AlphaChip (Nature 2021), ePlace (DAC Best Paper Nominee 2014), RL-CCD (DAC Best Paper 2023), INSTA (DAC Best Paper 2025), and C3PO (ASP-DAC Best Paper 2026), chip leads for Apple Silicon (multiple generations of iPhone and iPad) and Google (TPU, OpenTitan), and top researchers and engineers from Anthropic, Google DeepMind, Stanford, and MIT.
A self-improving chip design system is only as good as the silicon it produces, and silicon only counts once it has been tested, screened, and shipped. We are hiring a DFT engineer who treats testability as a first-class design discipline: someone who has architected the scan, MBIST, and boundary-scan...
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