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PhD Engineering Internship 2027

Riverlane · Boston, MA · On-site

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About Riverlane

Backed by Amadeus Capital Partners.

About the role

Delivering practical quantum error correction requires tightly integrated quantum and classical systems. Decoding algorithms must process large volumes of error data within demanding latency, bandwidth, compute and power constraints. As an engineering Intern, you will investigate the classical computing architectures needed to support scalable, fault-tolerant quantum computers. Your project will sit at the intersection of quantum error correction, computer architecture and hardware-software co-design. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Contribute to a research project focused on the classical systems and architectures required for scalable quantum error correction
  • Investigate methods for reducing the compute, communication, memory, latency or power requirements associated with QEC
  • Develop algorithms, simulations or architectural models to evaluate potential approaches
  • Explore trade-offs between decoding performance, logical error suppression and classical resource requirements
  • Consider how QEC workloads could be implemented across software, FPGA, ASIC or other computing architectures
  • Collaborate with researchers and engineers working across QEC theory, decoding, software and hardware
More about this role

Boston, US | Full-time | Fixed-term| Hybrid

Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in materials and climate science to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent, and passion.

Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.

Delivering practical quantum error correction requires tightly integrated quantum and classical systems. Decoding algorithms must process large volumes of error data within demanding latency, bandwidth, compute and power constraints.

As an engineering Intern, you will investigate the classical computing...

Read the full posting on Riverlane's site ↗

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