About the role
As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF–xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement. The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency across the hardware and software stack.
What they're looking for
- Experience owning system architecture decisions, technical requirements, interface definitions, and performance acceptance criteria across multiple hardware and software components
- Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and application software
- Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models
More about this role
At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.
Work Model: Onsite
Job Title: Director of Buffer & Memory Subsystem Architecture
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite
As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF–xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement. The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize...
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