Synopsys delivers comprehensive silicon-to-systems solutions that help innovators accelerate development, reduce risk, and drive breakthroughs. Backed by NEA.
About the role
You have spent years in the trenches of physical design, where the difference between a chip that tapes out clean and one that needs a respin often comes down to a timing path you caught at 2 AM or a power grid issue you debugged across three tool domains. You know that place and route is not just about closing timing, it is about understanding the tradeoffs between power, performance, and area well enough to make the right call when all three are pulling in different directions. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor's or Master's degree in Electrical Engineering with 2+ years of hands-on experience in physical design implementation
- Proficiency in place and route methodology, hierarchical design, and timing signoff using Synopsys Fusion Compiler or equivalent P&R tools
- Hands-on experience with physical design signoff tools such as PrimeTime for timing, StarRC for extraction, IC Validator for DRC/LVS, or RedHawk for power analysis
- Demonstrated ability to debug complex implementation issues across multiple domains including timing closure, power integrity, and physical verification
- Experience working on high-performance or low-power designs with a track record of contributing to PPA improvements and flow optimization
- Real tape-out experience on SoC, CPU, or GPU projects is a strong plus
More about this role
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years in the trenches of physical design, where the difference between a chip that tapes out clean and one that needs a respin often comes down to a timing path you caught at 2 AM or a power grid issue you debugged across three tool domains. You know that place and route is not just about closing timing, it is about understanding the tradeoffs between power, performance, and area well enough to make the right call when all three are pulling in different directions.
You are comfortable opening Fusion Compiler on Monday to close a complex hierarchical design and then jumping into PrimeTime or StarRC on Tuesday to figure out why a corner case is failing signoff. Real tape-out experience has taught you that the methodology matters as much as the...
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