Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in the U.S. with offices in Austin, Texas, and Silicon Valley, and global offices in Toronto, Belgrade, Seoul, Tokyo, and Bangalore, Tenstorrent brings together...
About the role
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs
- You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM
- You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows
- You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams
More about this role
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.
This role is hybrid, based out of Santa Clara, CA or...
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